The digital signal processor shall operate from 50–60 Hz AC power and shall be equipped with a 320-C19 16A IEC mains connector. The device shall operate safely from mains outlets delivering 100 – 240 VAC, and shall have a removable power cord. The device shall comply with FCC part 15 Class B requirements.
The digital signal processor shall have 24 bit, 48 kHz digital-to-analog converters and analog-to-digital converters. The processor shall be configurable using a drag-and-drop graphical user interface via the Signal Manager computer software application running on Microsoft Windows. Digital signal processing (DSP) resources shall be dynamically assigned and resource usage shall be displayed as part of the graphical user interface. DSP configurations shall be downloadable via RS232 or through a QSControl.net Audio Network System via the CM16a Amplifier Network Monitor. DSP configurations shall include any of the following functions, assignable anywhere in the signal chain: multiple parametric filters; multiple delays with a 20.83 microsecond increment and a 910 millisecond maximum; a compressor with available predictive delay for reduced signal distortion when applying fast attack times; an output peak limiter with available predictive delay for reduced signal distortion when applying fast attack times; high- and low-pass crossover filters including both 6, 12, 18 or 24 dB per octave Butterworth and 6, 12, 18 or 24 dB per octave Bessel along with 12 and 24 dB per octave Linkwitz-Riley filters; high- and low-pass shelf filters with variable corner frequency; signal mute and/ or attenuation in 0.1 dB steps; a 2➞1 post-crossover audio mixer; a signal splitter; pink and white noise generators; a variable-frequency tone generator; polarity reversal; a frequency response display; amplifier output indication with Clip and Protect functions. The digital signal processor shall have a minimum throughput delay of 1.0 milliseconds.
The front panel shall contain a blue Power indicator and a yellow Signal indicator. The front panel shall also have 7 LED signal present indicators. Analog program inputs shall be via two balanced Neutrik XLR / TRS Combo connectors With shield terminals connected to chassis ground. Inputs shall be electronically balanced, with input impedance of 8.3 kilohms balanced and 3.7 kilohms unbalanced, and a common mode rejection of at least 54 dB from 20 Hz to 20 kHz. . Input sensitivity shall be selectable, with the following options: .
Analog program outputs shall be via two male XLR connectors with all shield terminals connected to chassis ground; a - 6 dB pad shall be available. Outputs shall be electronically balanced, with output impedance of 600 ohms. Output level and units shall be selectable in software: maximum output level at full scale shall be 9.3Vrms (+21.5 dBu). The digital signal processor shall also have a female DB9 RS-232 port for setup and diagnostic functions.
Pin 9 of the DB-9 RS232 input shall be available as a single-ended contact closure input. Detection shall pull LOW (to ground, available on pin 5). Resistance for closure detection shall be less than 150 ohms; resistance for open detect TTL-compatible thresholds with 9V DC max input shall be less than 1.9 kilohms.
The digital signal processor shall be capable of meeting the following performance criteria: AES-17 -60 dB dynamic range of greater than 95 dB unweighted and 98 dB A weighted; THD + N of less than 0.007% from 20 Hz to 20 kHz at 1 dB below full scale output; inter-channel separation of better than 78 dB; frequency response of 20 Hz to 20 kHz ± 0.4 dB.
The digital signal processor’s chassis shall occupy one rack space. Depth from mounting surface to tips of rear supports shall be 14.9 in. (37.8 cm) with rack mount ears. When used without rack ears, the digital signal processor shall be 1.73 in. (4.39 cm) high, 18.9 in. (48.0 cm) wide and 13.7 in. (34.8 cm) deep. The weight of the digital signal processor shall not exceed 9.5 lb. (4.31 kg).
The digital signal processor shall be the QSC Audio Products DSP-30.
The digital signal processor shall operate from 15 VDC, 0.3 A power, supplied by either an external AC adapter such as the QSC DPX-1, by a compatible QSC CX 2-Channel Series host amplifier, or by a QSC DPX-4 rackmount chassis. The device shall comply with FCC part 15 Class B requirements.
The digital signal processor shall have 24 bit, 48 kHz digital-to-analog converters and analog-to-digital converters. The processor shall be configurable using a drag-and-drop graphical user interface via the Signal Manager computer software application running on Microsoft Windows. Digital signal processing (DSP) resources shall be dynamically assigned and resource usage shall be displayed as part of the graphical user interface. DSP configurations shall be downloadable via RS232 or through a QSControl.net Audio Network System via the CM16a Amplifier Network Monitor. DSP configurations shall include any of the following functions, assignable anywhere in the signal chain: multiple parametric filters; multiple delays with a 20.83 microsecond increment and a 910 millisecond maximum; a compressor with available predictive delay for reduced signal distortion when applying fast attack times; an output peak limiter with available predictive delay for reduced signal distortion when applying fast attack times; high- and low-pass crossover filters including both 6, 12, 18 or 24 dB per octave Butterworth and 6, 12, 18 or 24 dB per octave Bessel along with 12 and 24 dB per octave Linkwitz-Riley filters; high- and low-pass shelf filters with variable corner frequency; signal mute and/ or attenuation in 0.1 dB steps; a 2➞1 post-crossover audio mixer; a signal splitter; pink and white noise generators; a variable-frequency tone generator; polarity reversal; a frequency response display; amplifier output indication with Clip and Protect functions. The digital signal processor shall have a minimum throughput delay of 1.0 milliseconds.
The front panel shall contain a blue Power indicator and a yellow Signal indicator. The front panel shall also have 1 LED signal present indicators. Analog program inputs shall be via two female XLR connectors (one per channel). Inputs shall be electronically balanced, with input impedance of 8.3 kilohms balanced and 3.7 kilohms unbalanced, and a common mode rejection of at least 50 dB from 20 Hz to 20 kHz. . Input sensitivity shall be selectable, with the following options: 1.5Vrms = 5.7 dBu = 3.5 dBV; 4Vrms = 14.5 dBu = 12 dBV; 9Vrms = 21.3 dBu = 19.1 dBV; 18Vrms = 27.3 dBu = 25.1 dBV.
Analog program outputs shall be via two male XLR connectors . Program outputs shall also be available on a male HD-15 DataPort. The maximum qualified length of cable connection shall be 328 feet (100 m) when using QSC DP cable or 6 feet (1.83 m) when using other cable.
Pin 9 of the DB-9 RS232 input shall be available as a single-ended contact closure input. Detection shall pull LOW (to ground, available on pin 5). Resistance for closure detection shall be less than 150 ohms; resistance for open detect TTL-compatible thresholds with 9V DC max input shall be less than 1.9 kilohms.
The digital signal processor shall be capable of meeting the following performance criteria: AES-17 -60 dB dynamic range of greater than 104 dB unweighted and 107 dB A weighted for 1.5V sensitivity and dynamic range of 106 dB unweighted and 109 dB A weighted for all other sensitivities; THD + N of less than 0.02% from 20 Hz to 20 kHz at +4 dBu; inter-channel separation of better than 62 dB within the DataPort pair; frequency response of 20 Hz to 20 kHz ±0.7 dB via the XLR outputs and ±0.2 dB via the DataPort output.
The digital signal processor shall be 3.47 in. (8.81 cm) high, 3.35 in. (8.51 cm) wide and 2.05 in. (5.21 cm) deep. The weight of the digital signal processor shall not exceed 0.93 lb. (0.42 kg).
The digital signal processor shall be the QSC Audio Products DSP-4.
The digital signal processor shall operate from 15 VDC, 0.3 A power, supplied by either an external AC adapter such as the QSC DPX-1, by a compatible QSC CX 2-Channel Series host amplifier, or by a QSC DPX-4 rackmount chassis. The device shall comply with FCC part 15 Class B requirements.
The digital signal processor shall have 24 bit, 48 kHz digital-to-analog converters and analog-to-digital converters. The processor shall be configurable using a drag-and-drop graphical user interface via the Signal Manager computer software application running on Microsoft Windows. Digital signal processing (DSP) resources shall be dynamically assigned and resource usage shall be displayed as part of the graphical user interface. DSP configurations shall be downloadable via RS232 or through a QSControl.net Audio Network System via the CM16a Amplifier Network Monitor. DSP configurations shall include any of the following functions, assignable anywhere in the signal chain: multiple parametric filters; multiple delays with a 20.83 microsecond increment and a 910 millisecond maximum; a compressor with available predictive delay for reduced signal distortion when applying fast attack times; an output peak limiter with available predictive delay for reduced signal distortion when applying fast attack times; high- and low-pass crossover filters including both 6, 12, 18 or 24 dB per octave Butterworth and 6, 12, 18 or 24 dB per octave Bessel along with 12 and 24 dB per octave Linkwitz-Riley filters; high- and low-pass shelf filters with variable corner frequency; signal mute and/ or attenuation in 0.1 dB steps; a 2➞1 post-crossover audio mixer; a signal splitter; pink and white noise generators; a variable-frequency tone generator; polarity reversal; a frequency response display; amplifier output indication with Clip and Protect functions. The digital signal processor shall have a minimum throughput delay of 1.0 milliseconds.
The front panel shall contain a blue Power indicator and a yellow Signal indicator. Analog program inputs shall be via two phoenix/euro style connectors connectors (one per channel). Inputs shall be electronically balanced, with input impedance of 8.3 kilohms balanced and 3.7 kilohms unbalanced, and a common mode rejection of at least dB from 20 Hz to 20 kHz. Terminal pins shall be wired as follows: 1:+ / 2:- / 3:chassis ground. Input sensitivity shall be selectable, with the following options: 1.5Vrms = 5.7 dBu = 3.5 dBV; 4Vrms = 14.5 dBu = 12 dBV; 9Vrms = 21.3 dBu = 19.1 dBV; 13Vrms = 24.5 dBu = 22.2 dBV.
Analog program outputs shall be via two phoenix/euro 3-pin detachable terminal blocks. Program outputs shall also be available on a male HD-15 DataPort. The maximum qualified length of cable connection shall be 328 feet (100 m) when using QSC DP cable or 6 feet (1.83 m) when using other cable.
The digital signal processor shall be capable of meeting the following performance criteria: AES-17 -60 dB dynamic range of greater than 93 dB unweighted and 96 dB A weighted; THD + N of less than 0.01% from 20 Hz to 20 kHz at +4 dBu; inter-channel separation of better than 72 dB within the DataPort pair; frequency response of 20 Hz to 20 kHz ±0.7 dB via the 3-pin phoenix/euro style outputs and ±0.2 dB via the DataPort output.
The digital signal processor shall be 3.47 in. (8.81 cm) high, 3.37 in. (8.56 cm) wide and 1.37 in. (3.48 cm) deep. The weight of the digital signal processor shall not exceed 0.6 lb. (0.27 kg).
The digital signal processor shall be the QSC Audio Products DSP-3.
The digital signal processor shall operate from 50–60 Hz AC power and shall be equipped with a 320-C19 16A IEC mains connector. The device shall operate safely from mains outlets delivering 100 – 240 VAC, and shall have a removable power cord. The device shall comply with FCC part 15 Class B requirements.
The digital signal processor shall have 24 bit, 48 kHz digital-to-analog converters and analog-to-digital converters, and shall operate with 32-bit floating point processing. The digital signal processor shall be optimized for loudspeaker and amplifier management and shall have the ability to implement both IIR (Infinite Impulse Response) and FIR (Finite Impulse Response) filters. In addition to factory-optimized presets for specific loudspeaker models, the unit shall incorporate the following functions in DSP: six parametric filters; high- and low-pass shelving filters; subwoofer delay of zero to 50 milliseconds; array delay of zero to 20 milliseconds; user selection of stereo or mono-summed subwoofer outputs; adjustable subwoofer gain; automatic optimization for use with or without subwoofers; user-bypassable thermal protection for each transducer in the selected loudspeaker system; user-bypasssable excursion protection for each transducer in the selected loudspeaker system; user-selectable linked or independent control of stereo channel settings. The digital signal processor shall have a minimum throughput delay of 1.413 milliseconds.
The front panel shall contain a blue Power indicator, green/yellow/red LED input meters, a 2 line 16 character backlit LED display and a rotary encoder knob with Press-To-Select functionality.
Analog program inputs shall be via two female XLR connectors locking connectors with Pin 2 hot and shield terminals connected to chassis ground. Inputs shall be electronically balanced, with input impedance of 69.0 kilohms balanced and 11.0 kilohms unbalanced, and a common mode rejection of at least 75 dB from 20 Hz to 20 kHz. Input sensitivity shall be selectable, with the following options: 1.5Vrms = 5.7 dBu = 3.5 dBV; 3Vrms = 11.8 dBu = 9.5 dBV; 9Vrms = 21.3 dBu = 19.1 dBV; 18Vrms = 27.3 dBu = 25.1 dBV. Analog program outputs shall be via eight male XLR connectors with Pin 2 high and shield terminals connected to chassis ground. The rear panel shall include a USB type "B" port for loading new loudspeaker tunings.
The digital signal processor shall be capable of meeting the following performance criteria: AES-17 -60 dB dynamic range of greater than 104 dB unweighted and 107 dB A weighted, for all input sensitivities; THD + N of less than 0.006% from 20 Hz to 20 kHz at +4 dBu; inter-channel separation of better than 75dB; frequency response of 20 Hz to 20 kHz ± 0.1dB deviation from the target response for the selected amplifier and loudspeaker system.
The digital signal processor’s chassis shall occupy one rack space. Depth from mounting surface to the rear shall be 6.67 in. (16.9cm).
The digital signal processor shall be the QSC Audio Products SC28.